Pathology: Transition Fault
Found by: Transition Faults, Overshoot/Undershoot/Crosstalk:
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Summary Diagnosis and Suggested Solution Path


The probable cause of this stair step pattern is reflections from a poorly matched transmission line. It has the features of too high an impedance at the driver end.

If what you are measuring is the voltage at a receiver in a point to point routing topology with source series termination, then you should reduce the source series resistor at the driver so that the driver impedance and the resistor impedance match to the line impedance.

If there is no source series resistor than the output impedance of your driver may be too high to drive this transmission line; select another driver, add a line driver buffer, or use a higher impedance transmission line.

As a last resort, add a delay to the clock to wait out the first shelf, until the received signal level is well above the minimum input voltage level.


Reflections of signals on transmission lines are the most common, and easiest to fix, type of signal integrity problem. They arise from changes in the instantaneous impedance the signal sees on the line. Whenever a signal encounters a change in the instantaneous impedance, some of it will reflect, while the rest will continue at a different level.

The magnitude and sign of the reflected signal depends on the change in impedance. The reflection coefficient is the second impedance, minus the first, divided by their sum.

Every line has two ends, one at the driver and one at the receiver. Rarely is either end matched to the 50 Ohms of the transmission line, unless done on purpose.

The multiple bounces the signal can make between the impedances of the ends and the impedance of the interconnect cause distortions in the signal. When the driver impedance is lower than 50 Ohms and the receiver is high impedance, the waveform at the receiver shows ringing. This is usually fixed by increasing the series resistance of the driver, for example, by adding a series resistor. The series resistor plus the output impedance of the driver should equal the impedance of the line.

When the impedance of the driver is higher than 50 Ohms, less than half the full voltage swing is launched into the transmission line and when it reflects from the far end, the receiver will see a voltage below the full signal swing. It may take a few bounces of the signal to reach the full level. This is usually fixed by reducing the series resistance of the output driver.

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The noise signature of a point to point topology with source series resistance can be easily modeled in any version of SPICE, using the circuit below.



This is the schematic using Agilent’s ADS. The far end of the line, where the receiver would be, is open and is labeled as V_rx. This is where the scope probe would be located. The simulated received signal has the characteristic stair step behavior moving up to a final value, shown below.


In this specific case, what causes the stair stepping up are the multiple bounces between the high impedance of the receiver at the far end and the high impedance of the source series resistor.

In this simulation, the line impedance is 50 ohms and the combination of the driver output impedance and any added source series resistance is about 79 Ohms. This impedance could be due to a low impedance driver of 10 ohms, with a series resistor added to the board of 69 Ohms. The resistor should have been 39 Ohms, but the wrong value was actually assembled.

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Reflections are always due to an impedance mismatch at the driver or receiver with the line. Check the value of the source series resistor.

The time for the shelf at each level is the round trip time of flight for the transmission line. Take half the time interval for the shelf, as measured on the scope. This is the round trip delay. Divide this by 2. This is the time delay of the transmission line, in nsec. With a signal speed of roughly 6 inches per nsec, multiply this time delay, in nsec, by 6 and this should be roughly the physical length of the transmission line, in inches. This is a good check that the problem is reflection noise from mismatched terminations.

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All signal quality problems at the receiver can affect the timing of the received signal and create false triggering.

When the output impedance of the driver is too high, there may be a significant delay before the signal at the receiver rises above the minimum voltage to designate a 1 or a 0. This delay may push the received signal outside the set up or hold time. It can result in either a false reading or in metastablity.

When the output impedance of the driver is too low, there may be significant ringing. This can bring the signal at the receiver either below or above the threshold for a 1 or a 0.

The impact of the ringing or stair step behavior will depend on the relative timing of the received clock signal. Jitter in the clock may bring this reflection noise in and out of a problem area.

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Related Pathologies
Other anomalies with similar presentations.

All impedance mismatches the signal encounters can contribute to reflection noise and appear as shelves or ringing.

Distortions will also occur if the routing topology has branches, or long stubs. If stubs are longer in inches, than the rise time in nsec, distortions will occur. For example, if the rise time is 0.25 nsec and stubs are longer than 0.25 inches, ringing, shelves and distortion will happen.

Even in a well terminated source series topology, a shelf may appear in the measured signal at about half the signal swing level. This is usually due to measuring the voltage not at the receiver, but at a location some distance from the receiver. The duration of the shelf is the round trip time delay from the measurement location to the input of the receiver. If this shelf is measured, it is not an indication of a problem, but an artifact of where the measurement is taken.

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The general approach to minimize reflection noise is to:

  1. use controlled impedance interconnects
  2. route in a linear topology without branches and stubs
  3. use either a source series or far end parallel termination
  4. verify the signal quality expected before you commit to hardware using accurate driver models, accurate interconnect models and a circuit simulation tool such as SPICE.

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Related Topics

See also topics related to

  • shelf at the mid point of the voltage swing
  • ringing
  • branches
  • stubs
  • far end parallel termination


Author Information

Dr. Eric Bogatin
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